Altium

Design Rule Verification Report

Date:		7/15/2026
Time:		9:24:35 AM
Elapsed Time:		00:00:00
Filename:		C:\Users\susanna\OneDrive - Fermi National Accelerator Laboratory\Desktop\Reference Line Diagrams\LV Box\DC Power Supply Box\DCPowerSupplyBox.PcbDoc

Warnings:		0
Rule Violations:		0
PCB Health Issues:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=10mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=10mil) (Max=250mil) (Preferred=20mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=20mil) (Air Gap=20mil) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=20mil) (Disabled)(All)	0
Minimum Annular Ring (Minimum=10mil) (Disabled)(IsVia)	0
Hole Size Constraint (Min=10mil) (Max=250mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All)	0
Silk To Solder Mask (Clearance=10mil) (Disabled)(IsPad),(All)	0
Silk to Silk (Clearance=10mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0

PCB Health Issues	Count
Total	0